San Jose, Dec. 03, 2018 (GLOBE NEWSWIRE) -- MEDIA ALERT

WHO:  Andes Technology Corporation, a founding member of the RISC-V Foundation and leading supplier of small, low-power, high performance 32/64-bit embedded CPU and next generation RISC-V cores, today announced that it will participate in the 2018 RISC-V Summit Conference and Exhibition.

WHAT:  Andes Technology Corp. CTO & Senior VP of R&D, Charlie Su will present “Domain-Specific Acceleration via AndeStar V5 Processors.”  The presentation will describe a comprehensive solution to unlock potential domain specific acceleration in RISC-V. In addition, Senior Director of R&D/Architecture Division at Andes Technology, Chuanhua Chang will be a panelist for "RISC-V Security Ecosystem: Open for Business." The panel will discuss (1) the RISC-V security issues faced by a customer during implementation, (2) several commercial solutions to secure RISC-V, and (3) holistic test & verification best practices at the platform level.  Throughout the day in RISC-V Summit Exhibition area, Andes management and technical staff will be available to explain Andes’ RISC-V offerings and to answer attendees’ questions.

WHEN:  CTO & Senior VP of R&D, Charlie Su will present on Wednesday, 5 December 2018, from 1:10pm to 1:30pm in Exhibit Hall A-1 on the convention center first floor.  Senior Director of R&D/Architecture Division at Andes Technology, Chuanhua Chang’s panel will be on Tuesday, 4 December 2018, from 3:40pm to 4:20pm in Meeting Rooms 209/210 on the convention center second floor

WHERE:  Visit Andes Technology Corp. in booth 105 of the RISC-V Summit Exhibition area at the Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA 95054. To schedule a meeting e-mail america@andestech.com. 

Jonah McLeod
Andes Technology Corporation
510 449 8634
jonahm@andestech.com

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