Dublin, Nov. 26, 2018 (GLOBE NEWSWIRE) -- The "Qorvo QPF4006 39GHz GaN MMIC Front End Module Complete Teardown Report" report has been added to ResearchAndMarkets.com's offering.

In the last year, the increasing development of 5G has reshaped the Radio Frequency (RF) power industry landscape, driving the RF GaN market. Compared to existing silicon LDMOS and GaAs solutions, GaN devices are able to deliver the power/efficiency level required for next-generation high frequency telecom networks.

The Low Noise Amplifier (LNA) market is expected to deliver a 16% Compound Annual Growth Rate (CAGR) with the implementation of diversity modules, along with integration in Power Amplifier (PA) modules for handsets.

Qorvo was the first player to unveil a Front-End Module (FEM) for ultra-high band coverage based on GaN-on-SiC 0.15m technology.

The publisher unveils Qorvo's design, presenting our reverse costing of the QPF4006 39GHz GaN Monolithic Microwave Integrated Circuit (MMIC) FEM. The device is targeted for 5G base stations and terminals and combines, on the same die, a high linearity LNA, a low insertion-loss Transmit Receive (TR) switch and a high gain PA.

The QPF4006 is assembled in an air-cavity laminate package with embedded copper heat slug which demonstrates Qorvo's internal test and packaging capability.

The device is manufactured with 0.15m gate technology and AlGaN/GaN epitaxial structure deposited on a SiC substrate. Other than MMIC components it includes TaN resistors, SiN capacitors and three levels of metal interconnects including gold airbridges.

This report includes a detailed analysis of the packaging and the GaN on SiC transistor with optical and Scanning Electron Microscope (SEM) pictures. Moreover it provides a cost analysis for the complete device.

Key Topics Covered:

1. Overview/Introduction

• Executive Summary
• Reverse Costing Methodology

2. Company Profiles

• Qorvo

3. Physical Analysis

• Synthesis of the Physical Analysis
• Package Analysis
  • Package opening
  • Front-end module design
  • Package cross-section

• Die
  • Die view and dimensions
  • Die process
  • Die cross-section
  • Die process characteristics

4. Manufacturing Process

• Die Front-End Process
• Die Fabrication Unit
• Final Test and Packaging Fabrication Unit

5. Cost Analysis

• Summary of the Cost Analysis
• Yield Explanations and Hypotheses
• Gan on SiC die
  • Front-end cost
  • Die probe test, thinning and dicing
  • Wafer cost
  • Die cost

• Complete Power Stage
  • Packaging cost
  • Final test cost
  • Component cost

6. Price Analysis

• Estimated Sales Price

For more information about this report visit https://www.researchandmarkets.com/research/73csv6/teardown_report?w=12

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Related Topics: Semiconductor

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