Dublin, Nov. 15, 2019 (GLOBE NEWSWIRE) -- The "UnitedSiC Cascode JFET 650V Family" report has been added to ResearchAndMarkets.com's offering.

• This report provides a detailed manufacturing cost analysis of the JFET, the MOSFET and the package as well as the estimated selling price of each one of the five cascode components.
• Finally, this report compares the technological, physical parameters as well as the production cost and price of the Cascode JFET family's devices.
• A technology and cost comparison with a SiC MOSFET, with similar electrical performance, is also included.

The silicon carbide (SiC) power market is taking off and its value will approach US$2 billion by 2024.

The reason is that SiC-based device penetration is expanding in different applications. Taking advantage of this growing market, UnitedSiC, announced a strategic investment and long-term supply agreement with Analog Devices, Inc. (ADI) in March 2019.

UnitedSiC offers a large portfolio of SiC devices, mainly with its unique cascode co-pack configuration.

In this design, a Silicon MOSFET is combined with a SiC JFET in one package.

UnitedSiC offers two types of cascodes: UJ3C for ease of use when upgrading from a silicon device and UF3C for high-performance designs with faster switching. Moreover, it proposes the latest solution in die assembling; the silver sintering.

In this report, the author presents a deep technology analysis of the 650V cascode family: five components are analysed across the UJ3C and UF3C series, assembled in two different types of packages; with and without silver sintering.

Detailed optical pictures, scanning electron microscope cross-section, and energy-dispersive X-ray analyses are included to reveal UnitedSiC's technical choices at the microscopic level of the die designs.

Key Topics Covered

1. Introduction

• Executive Summary, Reverse Costing Methodology
• Glossary
• SiC Power Device Market

2. Company Profile

• UnitedSiC Profile, Portfolio and Technology

3. Physical Analysis

• Summary of the Physical Analysis
• UF3C065030K3S
• UF3C065030T3S
• UJ3C065030K3S
• UJ3C065080K3S
• UJ3C065080B3

4. For Each

• Package Analysis
• Package opening
• Package cross-section
• SiC JFET Die
• JFET die view and dimensions
• JFET die process and cross-section
• Si MOSFET Die
• MOSFET die view and dimensions
• MOSFET die process and cross-Section

5. Manufacturing Process

• JFET Die Front-End Process and Fabrication Unit
• MOSFET Die Front-End Process and Fabrication Unit
• Final Test and Packaging Fabrication Unit

6. Cost Analysis

• Overview of the Cost Analysis, Yield Explanations and Hypotheses
• JFET Die
• JFET front-end cost
• JFET die probe test, thinning and dicing
• JFET wafer and die cost
• MOSFET die
• MOSFET front-end cost
• MOSFET die probe test, thinning and dicing
• MOSFET wafer and die cost
• Complete Device
• Packaging cost
• Final test cost
• Component cost

7. Selling Price

• Estimation of Selling Price

8. Price Analysis

• Comparison of the Different Devices
• Comparison with SiC MOSFET with Similar Electrical Performance

For more information about this report visit https://www.researchandmarkets.com/r/n60ju2

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